DASIP 2021: Workshop on Design and Architectures for Signal and Image Processing

in conjunction with the 16th HiPEAC Conference

18-20 January 2021, Budapest, Hungary.

The Workshop on Design and Architectures for Signal and Image Processing (DASIP) provides an inspiring international forum for the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems. The workshop program will include keynote speeches and contributed paper sessions. The 14th edition will be held in conjunction with the 16th HiPEAC Conference in Budapest, Hungary, January 18-20, 2021.

List of topics

Prospective authors are invited to submit manuscripts on topics including, but not limited to:

Custom embedded, edge and cloud architectures and systems:

  • Machine learning and deep learning architectures for inference and training
  • Systems for autonomous vehicles : cars, drones, ships and space applications
  • Image processing and compression architectures
  • Smart cameras, security systems, behaviour recognition
  • Edge and cloud processing : special routing, configurable co-processors and low energy considerations
  • Real-time cryptography, secure computing, financial and personal data processing
  • Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computing
  • Biological data collection and analysis, bioinformatics
  • Personal digital assistants, natural language processing, wearable computing and implantable devices
  • Global navigation satellite and inertial navigation systems

Design Methods and Tools:

  • Design verification and fault tolerance
  • Embedded system security and security validation
  • System-level design and hardware/software co-design
  • High-level synthesis, logic synthesis, communication synthesis
  • Embedded real-time systems and real-time operating systems
  • Rapid system prototyping, performance analysis and estimation
  • Formal models, transformations, algorithm transformations and metrics

 

Development Platforms, Architectures and Technologies:

  • Embedded platforms for multimedia and telecommunication
  • Many-core and multi-processor systems, SoCs, and NoCs  
  • Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
  • Memory system and cache management
  • Asynchronous (self-timed) circuits and analog and mixed-signal circuits

Paper submission​

Authors should submit their full papers (up to 12 pages, single-column ACM format) in PDF through the EasyChair system. Please use the ACM template (Latex only, Master Article Template – sample-manuscript.tex).

Submitted papers are required to describe original unpublished work and must not be under consideration for publication elsewhere. Submissions must be fully anonymous, but authors should not hide previous work, instead, they need to make self-references in the third person.

Each submission will receive at least three independent double blind reviews from the members of our scientific committee. Authors will be encouraged to take the reviewers’ comments into account when they prepare the final versions of their papers and present the research during the workshop prior to its publication. The workshop proceedings will be published in the ACM International Conference Proceedings Series (ICPS). Paper and keynote presentation slides and tutorial documents will be made available to workshop attendees after the workshop (subject to confidentiality issues).

Important dates

  • Abstract submission deadline: October 11th, 2020
  • Paper submission deadline: October 18th, 2020
  • Notification of acceptance: November 22th, 2020
  • Camera ready papers: December 6th, 2020
  • Workshop : January 18-20, 2021

Committees

Steering Committee:

  • Bertrand Granado, Sorbonne Univeristy, France
  • Diana Goehringer, Technical University of Dresden, Germany
  • Eduardo de La Torre, Polytechnic University of Madrid, Spain
  • Guy Gogniat, University of Southern Brittany, France
  • Jean-Francois Nezan, INSA Rennes/ IETR laboratory, France
  • Jean-Pierre David, Polytechnique Montréal, Canada
  • Joao M. P. Cardoso, University of Porto, Portugal
  • Marek Gorgon, AGH University of Science and Technology, Poland
  • Michael Huebner, Brandenburg University of Technology, Germany
  • Paolo Meloni, University of Cagliari, Italy
  • Pierre Langlois, Polytechnique Montréal, Canada
  • Sebastien Pillement, University of Nantes, France
  • Tomasz Kryjak, AGH University of Science and Technology, Poland

Organising committee:

  • Tomasz Kryjak, AGH University of Science and Technology, Poland
  • Andrea Pinna, Sorbonne Univeristy, France

Venue

The Workshop on Design and Architectures for Signal and Image Processing will be held in conjunction with the 16th HiPEAC Conference in Budapest, Hungary, January 18-20, 2021.

Contact

All questions about the workshop and submissions should be emailed to Tomasz Kryjak or Andrea Pinna.

Past events

  • DASIP 2019 (13th), Polytechnique Montréal, Canada
  • DASIP 2018 (12th), University of Porto, Portugal
  • DASIP 2017 (11th), Technical University of Dresden, Germany
  • DASIP 2016 (10th), RISA/INRIA Rennes, France,
  • DASIP 2015 (9th), AGH University of Science and Technology, Krakow, Poland
  • DASIP 2014 (8th), Autonomous University of Madrid, Spain
  • DASIP 2013 (7th), University of Cagliari, Italy
  • DASIP 2012 (6th), Karlsruhe Institute of Technology, Germany
  • DASIP 2011 (5th), Tampere University of Technology, Finland
  • DASIP 2010 (4th), University of Edinburgh, UK
  • DASIP 2009 (3rd), Sophia Antipolis, France
  • DASIP 2008 (2nd), Brussels, Belgium
  • DASIP 2007 (1st), Grenoble, France